VGSM-II ME SIM Interface
From VoiSmart Open Source Wiki
The vGSM-II card decuples the GSM module (ME) to SIM interface from the SIM itself through the FPGA chip. When the FPGA R_SIM_ROUTE register is programmed for ME to UART connection, the external override is disabled and the ME-SIM interface if fully controlled by the internal UART, otherwise the internal UART is put in a receive-only state and it cannot interfere with the external signals.
The vgsm2 Linux driver registers one character device for each ME-SIM interface with the vgsm2_mesimX or vgsm/mesim_X name.
The character device can be treated as a serial port using the termios(3) functions such as tcsetattr(3)
The baud rate should be set according to the frequency and divisor negotiated with the ME. Currently the UART receives a fixed clock and cannot adapt automatically to the SIM clock frequency changes. In future versions may implement such feature.
The SIM's I/O signal is fed to the UART receive and transmit pins by means of a rx/tx interlock that will separate received and transmitted messages by monitoring who starts a transmission and locking the signal direction until a guard time after the last bit has elapsed.
The other SIM's signals are connected according to the following table:
- RTS => CCIN
- CTS <= CCRST
- DTR <= CCVCC
